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FEATURES Full 16-Bit Performance 5 V Single Supply Operation Low Power Short Settling Time Unbuffered Voltage Output Capable of Driving 60 k Loads Directly SPITM/QSPITM/MICROWIRETM-Compatible Interface Standards Power-On Reset Clears DAC Output to 0 V (Unipolar Mode) Schmitt Trigger Inputs for Direct Optocoupler Interface APPLICATIONS Digital Gain and Offset Adjustment Automatic Test Equipment Data Acquisition Systems Industrial Process Control
5 V, Serial-Input Voltage-Output, 16-Bit DACs AD5541/AD5542
FUNCTIONAL BLOCK DIAGRAMS
VDD
AD5541
REF 16-BIT DAC VOUT
AGND CS DIN SCLK CONTROL LOGIC SERIAL INPUT REGISTER 16-BIT DATA LATCH
DGND
VDD
AD5542
RINV REFF 16-BIT DAC REFS
RFB RFB INV
VOUT AGNDF
GENERAL DESCRIPTION
CS LDAC SCLK DIN CONTROL LOGIC
The AD5541 and AD5542 are single, 16-bit, serial input, voltage output DACs that operate from a single 5 V 10% supply. The AD5541 and AD5542 utilize a versatile 3-wire interface that is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. These DACs provide 16-bit performance without any adjustments. The DAC output is unbuffered, which reduces power consumption and offset errors contributed to by an output buffer. The AD5542 can be operated in bipolar mode generating a VREF output swing. The AD5542 also includes Kelvin sense connections for the reference and analog ground pins to reduce layout sensitivity. The AD5541 and AD5542 are available in an SO package.
16-BIT DATA LATCH AGNDS SERIAL INPUT REGISTER
DGND
PRODUCT HIGHLIGHTS
1. Single Supply Operation. The AD5541 and AD5542 are fully specified and guaranteed for a single 5 V 10% supply. 2. Low Power Consumption. These parts consume typically 1.5 mW with a 5 V supply. 3. 3-Wire Serial Interface. 4. Unbuffered output capable of driving 60 k loads. This reduces power consumption as there is no internal buffer to drive. 5. Power-On Reset circuitry.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD5541/AD5542-SPECIFICATIONS T = T
Parameter STATIC PERFORMANCE Resolution Relative Accuracy, INL Min 16 Typ Max 0.5 0.5 0.5 0.5 -1.5 0.1 0.3 0.05 1.0 2.0 4.0 1.0 1.5 5 7 1 2
(VDD = 5 V 10%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications A MIN to TMAX, unless otherwise noted.)
Unit Bits LSB LSB LSB LSB LSB LSB LSB ppm/C LSB LSB ppm/C / % LSB LSB ppm/C V V s V/s nV-s nV-s k LSB V k k A V V pF V MHz mV p-p dB pF pF All 1s Loaded All 0s Loaded, VREF = 1 V p-p at 100 kHz Code 0000 Hex Code FFFF Hex Test Condition
Differential Nonlinearity Gain Error Gain Error Temperature Coefficient Zero Code Error Zero Code Temperature Coefficient AD5542 Bipolar Resistor Matching Bipolar Zero Offset Error Bipolar Zero Temperature Coefficient OUTPUT CHARACTERISTICS Output Voltage Range Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough DAC Output Impedance Power Supply Rejection Ratio DAC REFERENCE INPUT Reference Input Range Reference Input Resistance2 LOGIC INPUTS Input Current VINL, Input Low Voltage VINH, Input High Voltage Input Capacitance3 Hysteresis Voltage3 REFERENCE Reference -3 dB Bandwidth Reference Feedthrough Signal-to-Noise Ratio Reference Input Capacitance POWER REQUIREMENTS VDD IDD Power Dissipation 2.0 9 7.5 0 -VREF
L, C Grades B, J Grades A Grade Guaranteed Monotonic J Grade TA = 25C TA = 25C
1.000 0.0015 0.0076 1 5 7 0.2 VREF - 1 LSB VREF - 1 LSB 1 25 10 10 6.25
RFB/RINV, Typically RFB = RINV = 28 k Ratio Error TA = 25C
1.0 VDD
Unipolar Operation AD5542 Bipolar Operation to 1/2 LSB of FS, CL = 10 pF CL = 10 pF, Measured from 0% to 63% 1 LSB Change Around the Major Carry All 1s Loaded to DAC, VREF = 2.5 V Tolerance Typically 20% VDD 10%
Unipolar Operation AD5542, Bipolar Operation
1 0.8 2.4 10 0.4 1.3 1 92 75 120 4.50 0.3 1.5 5.50 1.1 6.05
V mA mW
NOTES 1 Temperature ranges are as follows: A, B, C Versions: -40C to +85C. J, L Versions: 0C to 70C. 2 Reference input resistance is code-dependent, minimum at 8555 hex. 3 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
-2-
REV. A
AD5541/AD5542 TIMING CHARACTERISTICS1, 2 otherwise noted.)
Parameter fSCLK t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 Limit at TMIN, TMAX All Versions 25 40 20 20 15 15 35 20 15 0 30 30 30
(VDD = 5 V
5%, VREF = 2.5 V, AGND = DGND = 0 V. All specifications TA = TMIN to TMAX, unless
Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
Description SCLK Cycle Frequency SCLK Cycle Time SCLK High Time SCLK Low Time CS Low to SCLK High Setup CS High to SCLK High Setup SCLK High to CS Low Hold Time SCLK High to CS High Hold Time Data Setup Time Data Hold Time LDAC Pulsewidth CS High to LDAC Low Setup CS High Time Between Active Periods
NOTES 1 Guaranteed by design. Not production tested. 2 Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (V IL + VIH)/2. Specifications subject to change without notice.
t1
SCLK
t6 t4
CS
t2
t3 t7
t5
t 12 t8 t9
DB15 DB0
DIN
t 11
LDAC* *AD5542 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
t 10
Figure 1. Timing Diagram
REV. A
-3-
AD5541/AD5542
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6 V Digital Input Voltage to DGND . . . . . -0.3 V to VDD + 0.3 V VOUT to AGND . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3 V AGND, AGNDF, AGNDS to DGND . . . . . -0.3 V to +0.3 V Input Current to Any Pin Except Supplies . . . . . . . . 10 mA Operating Temperature Range Industrial (A, B, C Versions) . . . . . . . . . . . -40C to +85C Commercial (J, L Versions) . . . . . . . . . . . . . . . 0C to 70C Storage Temperature Range . . . . . . . . . . . . -65C to +150C
Maximum Junction Temperature, (TJ max) . . . . . . . . . 150C Package Power Dissipation . . . . . . . . . . . . . (TJ max - TA)/JA Thermal Impedance JA SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . 149.5C/W SOIC (R-14) . . . . . . . . . . . . . . . . . . . . . . . . . . 104.5C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD5541CR AD5541LR AD5541BR AD5541JR AD5541AR AD5542CR AD5542LR AD5542BR AD5542JR AD5542AR
INL 1 LSB 1 LSB 2 LSB 2 LSB 4 LSB 1 LSB 1 LSB 2 LSB 2 LSB 4 LSB
DNL 1 LSB 1 LSB 1 LSB 1.5 LSB 1 LSB 1 LSB 1 LSB 1 LSB 1.5 LSB 1 LSB
Temperature Range -40C to +85C 0C to 70C -40C to +85C 0C to 70C -40C to +85C -40C to +85C 0C to 70C -40C to +85C 0C to 70C -40C to +85C
Package Description 8-Lead Small Outline IC 8-Lead Small Outline IC 8-Lead Small Outline IC 8-Lead Small Outline IC 8-Lead Small Outline IC 14-Lead Small Outline IC 14-Lead Small Outline IC 14-Lead Small Outline IC 14-Lead Small Outline IC 14-Lead Small Outline IC
Package Option SO-8 SO-8 SO-8 SO-8 SO-8 R-14 R-14 R-14 R-14 R-14
Die Size = 80 x 139 = 11,120 sq mil; Number of Transistors = 1,230.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5541/AD5542 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. A
AD5541/AD5542
AD5541 PIN FUNCTION DESCRIPTIONS
Mnemonic VOUT AGND REF CS SCLK DIN DGND VDD
Pin No. 1 2 3 4 5 6 7 8
Description Analog Output Voltage from the DAC. Ground Reference Point for Analog Circuitry. This is the voltage reference input for the DAC. Connect to external 2.5 V reference. Reference can range from 2 V to VDD. This is a logic input signal. The chip select signal is used to frame the serial data input. Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK. Digital Ground. Ground reference for digital circuitry. Analog Supply Voltage, 5 V 10%.
AD5542 PIN CONFIGURATION SOIC
AD5541 PIN CONFIGURATION SOIC
VOUT 1 AGND 2
8
VDD DGND
RFB 1 VOUT 2 AGNDF 3 AGNDS 4
14 13 12
VDD INV DGND LDAC
AD5541
7
TOP VIEW REF 3 (Not to Scale) 6 DIN CS 4
5
SCLK
AD5542
11
TOP VIEW REFS 5 (Not to Scale) 10 DIN REFF 6 CS 7
9 8
NC SCLK
NC = NO CONNECT
AD5542 PIN FUNCTION DESCRIPTIONS
Mnemonic RFB VOUT AGNDF AGNDS REFS REFF CS SCLK NC DIN LDAC DGND INV VDD
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Description Feedback Resistor. In bipolar mode connect this pin to external op amp output. Analog Output Voltage from the DAC. Ground Reference Point for Analog Circuitry (Force). Ground Reference Point for Analog Circuitry (Sense). This is the voltage reference input (sense) for the DAC. Connect to external 2.5 V reference. Reference can range from 2 V to VDD. This is the voltage reference input (force) for the DAC. Connect to external 2.5 V reference. Reference can range from 2 V to VDD. This is a logic input signal. The chip select signal is used to frame the serial data input. Clock input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%. No Connect. Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK. LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the input register. Digital Ground. Ground reference for digital circuitry. Connected to the Internal Scaling Resistors of the DAC. Connect INV pin to external op amps inverting input in bipolar mode. Analog Supply Voltage, 5 V 10%.
REV. A
-5-
AD5541/AD5542
TERMINOLOGY Relative Accuracy Digital-to-Analog Glitch Impulse
For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL versus code plot can be seen in Figure 2.
Differential Nonlinearity
Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition. A plot of the glitch impulse is shown in Figure 15.
Digital Feedthrough
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. Figure 3 illustrates a typical DNL versus code plot.
Gain Error
Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal.
Gain Error Temperature Coefficient
Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. CS is held high, while the CLK and DIN signals are toggled. It is specified in nV-s and is measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. A typical plot of digital feedthrough is shown in Figure 14.
Power Supply Rejection Ratio
This is a measure of the change in gain error with changes in temperature. It is expressed in ppm/C.
Zero Code Error
This specification indicates how the output of the DAC is affected by changes in the power supply voltage. Power-supply rejection ratio is quoted in terms of % change in output per % change in VDD for full-scale output of the DAC. VDD is varied by 10%.
Reference Feedthrough
Zero code error is a measure of the output error when zero code is loaded to the DAC register.
Zero Code Temperature Coefficient
This is a measure of the change in zero code error with a change in temperature. It is expressed in mV/C.
This is a measure of the feedthrough from the VREF input to the DAC output when the DAC is loaded with all 0s. A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough is expressed in mV p-p.
-6-
REV. A
Typical Performance Characteristics- AD5541/AD5542
0.50 DIFFERENTIAL NONLINEARITY - LSB VDD = 5V VREF = 2.5V 0.50 VDD = 5V VREF = 2.5V 0.25
INTEGRAL NONLINEARITY - LSB
0.25
0
0
-0.25
-0.25
-0.50
-0.75
-0.50 0 8192 16384 24576 32768 40960 49152 57344 65536 CODE
0
8192
16384 24576 32768 40960 49152 57344 65536 CODE
Figure 2. Integral Nonlinearity vs. Code
Figure 5. Differential Nonlinearity vs. Code
0.25
DIFFERENTIAL NONLINEARITY - LSB
0.75
INTEGRAL NONLINEARITY - LSB
VDD = 5V VREF = 2.5V 0
VDD = 5V VREF = 2.5V 0.50
-0.25
0.25
-0.50
0
-0.75
-0.25
-1.00 -60
-40
-20
0
20
40
60
80
100
120
140
-0.50 -60
-40
-20
0
20
40
60
80
100
120
140
TEMPERATURE - C
TEMPERATURE - C
Figure 3. Integral Nonlinearity vs. Temperature
Figure 6. Differential Nonlinearity vs. Temperature
0.50 VREF = 2.5V TA = 25 C 0.25
0.75 VDD = 5V TA = 25 C 0.50
DNL
LINEARITY ERROR - LSB
LINEARITY ERROR - LSB
DNL
0
0.25
-0.25
0 INL -0.25
-0.50 INL -0.75
-0.50
2 3 4 5 SUPPLY VOLTAGE - V 6 7
0
1
2 3 4 REFERENCE VOLTAGE - V
5
6
Figure 4. Linearity Error vs. Supply Voltage
Figure 7. Linearity Error vs. Reference Voltage
REV. A
-7-
AD5541/AD5542
0 VDD = 5V VREF = 2.5V 0.75 VDD = 5V VREF = 2.5V
ZERO-CODE ERROR - LSB
-40 -20 0 20 40 60 80 100 120 140
GAIN ERROR - LSB
-0.25
0.50
-0.50
0.25
-0.75 -60
0 -60
-40
-20
0
20
40
60
80
100
120
140
TEMPERATURE - C
TEMPERATURE - C
Figure 8. Gain Error vs. Temperature
Figure 11. Zero-Code Error vs. Temperature
250 VDD = 5V VLOGIC = 5V VREF = 2.5V
A
450 TA = 25 C 400
A SUPPLY CURRENT -
350
SUPPLY CURRENT -
200
300
REFERENCE VOLTAGE VDD = 5V
SUPPLY VOLTAGE VREF = 2.5V
250
200
150 -40
-20
0
20
40
60
80
100
120
150
0
1
2
TEMPERATURE - C
3 VOLTAGE - V
4
5
6
Figure 9. Supply Current vs. Temperature
Figure 12. Supply Current vs Reference Voltage or Supply Voltage
400 VDD = 5V VREF = 2.5V TA = 25 C
300 5555H 8555H 250 0555H BIPOLAR MODE 200 VDD = 5V VREF = 2.5V TA = 25 C
A
300
REFERENCE CURRENT -
SUPPLY CURRENT -
A
350
250
150 UNIPOLAR MODE 100
200
150
50 0 1 3 2 DIGITAL INPUT VOLTAGE - V 4 5 0 8192 16384 24576 32768 40960 49152 CODE 57344 65536
Figure 10. Supply Current vs. Digital Input Voltage
Figure 13. Reference Current vs. Code
-8-
REV. A
AD5541/AD5542
100 90
CLOCK (5V/DIV)
VREF = 2.5V VDD = 5V TA = 25 C
2s/DIV
100 90
CS (5V/DIV) 10pF 50pF 100pF 200pF
VOUT (50mV/DIV)
10 0%
10 0%
VREF = 2.5V VDD = 5V TA = 25 C VOUT (0.5V/DIV)
2 s/DIV
Figure 14. Digital Feedthrough
VREF = 2.5V VDD = 5V TA = 25 C CS (5V/DIV)
Figure 16. Large Signal Settling Time
VREF = 2.5V VDD = 5V TA = 25 C
100 90
100 90
VOUT (1V/DIV)
VOUT (0.1V/DIV)
10 0%
10 0%
VOUT (50mV/DIV) GAIN = -216 1LSB = 8.2mV
2s/DIV
0.5 s/DIV
Figure 15. Digital-to-Analog Glitch Impulse
GENERAL DESCRIPTION
Figure 17. Small Signal Settling Time
The AD5541/AD5542 are single, 16-bit, serial input, voltage output DACs. They operate from a single supply ranging from 2.7 V to 5 V and consume typically 300 mA with a supply of 5 V. Data is written to these devices in a 16-bit word format, via a 3- or 4-wire serial interface. To ensure a known power-up state, these parts were designed with a power-on reset function. In unipolar mode, the output is reset to 0 V, while in bipolar mode, the AD5542 output is set to -VREF. Kelvin sense connections for the reference and analog ground are included on the AD5542.
Digital-to-Analog Section
With this type of DAC configuration, the output impedance is independent of code, while the input impedance seen by the reference is heavily code dependent. The output voltage is dependent on the reference voltage as shown in the following equation.
VOUT = VREF x D 2N
where D is the decimal data word loaded to the DAC register and N is the resolution of the DAC. For a reference of 2.5 V, the equation simplifies to the following.
VOUT = 2.5 x D 65, 536
The DAC architecture consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 18. The DAC architecture of the AD5541/AD5542 is segmented. The four MSBs of the 16-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of 15 matched resistors to either AGND or VREF. The remaining 12 bits of the data word drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder network.
R R VOUT 2R 2R S0 VREF 2R S1 2R S11 2R E1 2R E2 2R E15
giving a VOUT of 1.25 V with midscale loaded, and 2.5 V with full-scale loaded to the DAC. The LSB size is VREF/65,536.
Serial Interface
12-BIT R-2R LADDER
FOUR MSB's DECODED INTO 15 EQUAL SEGMENTS
Figure 18. DAC Architecture
The AD5541 and AD5542 are controlled by a versatile 3-wire serial interface, which operates at clock rates up to 25 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. The timing diagram can be seen in Figure 1. Input data is framed by the chip select input, CS. After a high-to-low transition on CS, data is shifted synchronously and latched into the input register on the rising edge of the serial clock, SCLK. Data is loaded MSB first in 16-bit words. After 16 data bits have been loaded into the serial input register, a low-to-high transition on CS transfers the contents of the shift register to the DAC. Data can only be loaded to the part while CS is low. -9-
REV. A
AD5541/AD5542
The AD5542 has an LDAC function that allows the DAC latch to be updated asynchronously by bringing LDAC low after CS goes high. LDAC should be maintained high while data is written to the shift register. Alternatively, LDAC may be tied permanently low to update the DAC synchronously. With LDAC tied permanently low, the rising edge of CS will load the data to the DAC.
Unipolar Output Operation
+2.5V +5V 0.1 F 10 F 0.1 F
RFB SERIAL INTERFACE VDD CS DIN SCLK LDAC DGND RINV REFF REFS RFB INV OUT
+5V
These DACs are capable of driving unbuffered loads of 60 k. Unbuffered operation results in low-supply current, typically 300 A, and a low-offset error. The AD5541 provides a unipolar output swing ranging from 0 V to VREF. The AD5542 can be configured to output both unipolar and bipolar voltages. Figure 19 shows a typical unipolar output voltage circuit. The code table for this mode of operation is shown in Table I.
+5V +2.5V 10 F
AD5541/AD5542
AGNDF AGNDS -5V EXTERNAL OP AMP
BIPOLAR OUTPUT
Figure 20. Bipolar Output (AD5542 Only)
Table II. Bipolar Code Table
DAC Latch Contents MSB LSB 1111 1111 1111 1111 1000 0000 0000 0001 1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000
UNIPOLAR OUTPUT
Analog Output +VREF x (32,767/32,768) +VREF x (1/32,768) 0V -VREF x (1/32,768) -VREF x (32,768/32,768) = -VREF
0.1 F
0.1 F
SERIAL INTERFACE
VDD CS DIN SCLK LDAC*
REF(REFF*)
REFS*
AD5541/AD5542
OUT
AD820/ OP196
EXTERNAL OP AMP
DGND * AD5542 ONLY
AGND
Assuming a perfect reference, the worst-case bipolar output voltage may be calculated from the following equation. Bipolar Mode Worst-Case Output
VOUT - BIP =
Figure 19. Unipolar Output
Table I. Unipolar Code Table
[(V
OUT -UNI
+ VOS 2 + RD - VREF 1 + RD
)( ) 1 + (2 + RD) / A
(
)]
DAC Latch Contents MSB LSB 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000
Analog Output VREF x (65,535/65,536) VREF x (32,768/65,536) = 1/2 VREF VREF x (1/65,536) 0V
where VOS = External Op Amp Input Offset Voltage RD = RFB and RIN Resistor Matching Error A = Op Amp Open-Loop Gain
Output Amplifier Selection
Assuming a perfect reference, the worst case output voltage may be calculated from the following equation. Unipolar Mode Worst-Case Output
VOUT -UNI =
where VOUT-UNI D VREF VGE VZSE INL
D 216
x (VREF + VGE ) + VZSE + INL
For bipolar mode, a precision amplifier should be used, supplied from a dual power supply. This will provide the VREF output. In a single-supply application, selection of a suitable op amp may be more difficult as the output swing of the amplifier does not usually include the negative rail, in this case AGND. This can result in some degradation of the specified performance unless the application does not use codes near zero. The selected op amp needs to have very low-offset voltage, (the DAC LSB is 38 V with a 2.5 V reference), to eliminate the need for output offset trims. Input bias current should also be very low as the bias current multiplied by the DAC output impedance (approximately 6K) will add to the zero code error. Rail-to-rail input and output performance is required. For fast settling, the slew rate of the op amp should not impede the settling time of the DAC. Output impedance of the DAC is constant and code-independent, but in order to minimize gain errors, the input impedance of the output amplifier should be as high as possible. The amplifier should also have a 3 dB bandwidth of 1 MHz or greater. The amplifier adds another time constant to the system, hence increasing the settling time of the output. A higher 3 dB amplifier bandwidth results in a shorter effective settling time of the combined DAC and amplifier.
Force Sense Amplifier Selection
= Unipolar Mode Worst-Case Output = Code Loaded to DAC = Reference Voltage Applied to Part = Gain Error in Volts = Zero Scale Error in Volts = Integral Nonlinearity in Volts
Bipolar Output Operation
With the aid of an external op amp, the AD5542 may be configured to provide a bipolar voltage output. A typical circuit of such operation is shown in Figure 20. The matched bipolar offset resistors RFB and RINV are connected to an external op amp to achieve this bipolar output swing, typically RFB = RINV = 28 k. Table II shows the transfer function for this output operating mode. Also provided on the AD5542 are a set of Kelvin connections to the analog ground inputs.
These amplifiers will be single-supply, low-noise amplifiers. A low-output impedance at high frequencies is preferred as they need to be able to handle dynamic currents of up to 20 mA. REV. A
-10-
AD5541/AD5542
Reference and Ground AD5541/AD5542 to 68HC11 Interface
As the input impedance is code-dependent, the reference pin should be driven from a low-impedance source. The AD5541/ AD5542 operates with a voltage reference ranging from 2 V to VDD. References below 2 V will result in reduced accuracy. The DAC's full-scale output voltage is determined by the reference. Tables I and II outline the analog output voltage or particular digital codes. For optimum performance, Kelvin sense connections are provided on the AD5542. If the application doesn't require separate force and sense lines, they should be tied together close to the package to minimize voltage drops between the package leads and the internal die.
Power-On Reset
Figure 22 shows a serial interface between the AD5541/AD5542 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC, while the MOSI output drives the serial data lines SDIN. CS signal is driven from one of the port lines. The 68HC11 is configured for master mode; MSTR = 1, CPOL = 0, and CPHA = 0. Data appearing on the MOSI output is valid on the rising edge of SCK.
PC6 LDAC** CS DIN SCLK
68HC11/ 68L11*
PC7 MOSI SCK
AD5541/ AD5542*
These parts have a power-on reset function to ensure the output is at a known state upon power-up. On power-up, the DAC register contains all zeros, until data is loaded from the serial register. However, the serial register is not cleared on power-up, so its contents are undefined. When loading data initially to the DAC, 16 bits or more should be loaded to prevent erroneous data appearing on the output. If more than 16 bits are loaded, the last 16 are kept, and if less than 16 are loaded, bits will remain from the previous word. If the AD5541/AD5542 needs to be interfaced with data shorter than 16 bits, the data should be padded with zeros at the LSBs.
Power Supply and Reference Bypassing
*ADDITIONAL PINS OMITTED FOR CLARITY. **AD5542 ONLY
Figure 22. AD5541/AD5542 to 68HC11/68L11 Interface
AD5541/AD5542 to MICROWIRE Interface
Figure 23 shows an interface between the AD5541/AD5542 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and into the AD5541/ AD5542 on the rising edge of the serial clock. No glue logic is required as the DAC clocks data into the input shift register on the rising edge.
CS CS DIN SCLK
For accurate high-resolution performance, it is recommended that the reference and supply pins be bypassed with a 10 F tantalum capacitor in parallel with a 0.1 F ceramic capacitor.
MICROPROCESSOR INTERFACING
MICROWIRE*
SO SCLK
AD5541/ AD5542*
*ADDITIONAL PINS OMITTED FOR CLARITY.
Microprocessor interfacing to the AD5541/AD5542 is via a serial bus that uses standard protocol compatible with DSP processors and microcontrollers. The communications channel requires a 3-wire interface consisting of a clock signal, a data signal and a synchronization signal. The AD5541/AD5542 requires a 16-bit data word with data valid on the rising edge of SCLK. The DAC update may be done automatically when all the data is clocked in or it may be done under control of LDAC (AD5542 only).
AD5541/AD5542-ADSP-2101/ADSP-2103 Interface
Figure 23. AD5541/AD5542 to MICROWIRE Interface
AD5541/AD5542 to 80C51/80L51 Interface
A serial interface between the AD5541/AD5542 and the 80C51/ 80L51 microcontroller is shown in Figure 24. TxD of the microcontroller drives the SCLK of the AD5541/AD5542, while RxD drives the serial data line of the DAC. P3.3 is a bit programmable pin on the serial port which is used to drive CS. The 80C51/80L51 provides the LSB first, while the AD5541/ AD5542 expects the MSB of the 16-bit word first. Care should be taken to ensure the transmit routine takes this into account. When data is to be transmitted to the DAC, P3.3 is taken low. Data on RxD is valid on the falling edge of TxD, so the clock must be inverted as the DAC clocks data into the input shift register on the rising edge of the serial clock. The 80C51/80L51 transmits its data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. As the DAC requires a 16-bit word, P3.3 must be left low after the first eight bits are transferred, and brought high after the second byte is transferred. LDAC on the AD5542 may also be controlled by the 80C51/80L51 serial port output by using another bit programmable pin, P3.4.
P3.4 LDAC** CS DIN SCLK
Figure 21 shows a serial interface between the AD5541/AD5542 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set to operate in the SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 is programmed through the SPORT control register and should be configured as follows: Internal Clock Operation, Active Low Framing, 16-Bit Word Length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. As the data is clocked out on each rising edge of the serial clock, an inverter is required between the DSP and the DAC, because the AD5541/AD5542 clocks data in on the falling edge of the SCLK.
FO LDAC** CS DIN SCLK
ADSP-2101/ ADSP-2103*
TFS DT SCLK
AD5541/ AD5542*
80C51/ 80L51*
P3.3 RxD TxD
AD5541/ AD5542*
*ADDITIONAL PINS OMITTED FOR CLARITY. **AD5542 ONLY
Figure 21. AD5541/AD5542 to ADSP-2101/ADSP-2103 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY. **AD5542 ONLY
Figure 24. AD5541/AD5542 to 80C51/80L51 Interface
REV. A
-11-
AD5541/AD5542
APPLICATIONS Optocoupler interface Decoding Multiple AD5541/AD5542s
5V REGULATOR POWER
10 F
0.1 F
AD5541/AD5542 SCLK CS VOUT
VDD 10k SCLK SCLK VDD
DIN VDD
DIN SCLK
ENABLE
VDD
EN DECODER
AD5541/AD5542 CS DIN SCLK VOUT
AD5541/AD5542
10k CS CS VOUT
CODED ADDRESS
DGND AD5541/AD5542 CS DIN SCLK VOUT
VDD 10k DIN DIN GND
AD5541/AD5542 CS
Figure 25. AD5541/AD5542 in an Optocoupler Interface
DIN SCLK
VOUT
Figure 26. Addressing Multiple AD5541/AD5542s
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SO (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 5 4
14-Lead SO (R-14)
0.3444 (8.75) 0.3367 (8.55) 0.1574 (4.00) 0.1497 (3.80)
14 1 8 7
0.1574 (4.00) 0.1497 (3.80) PIN 1
1
0.2440 (6.20) 0.2284 (5.80)
0.2440 (6.20) 0.2284 (5.80)
PIN 1
0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19)
0.0196 (0.50) 0.0099 (0.25)
45
0.050 (1.27) BSC
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) 0.0099 (0.25)
45
0.0500 (1.27) 0.0160 (0.41)
0.0098 (0.25) 0.0040 (0.10)
8 0.0192 (0.49) SEATING 0.0099 (0.25) 0 PLANE 0.0138 (0.35) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
-12-
REV. A
PRINTED IN U.S.A.
C3713-8-10/99
The digital inputs of the AD5541/AD5542 are Schmitttriggered, so they can accept slow transitions on the digital input lines. This makes these parts ideal for industrial applications where it may be necessary that the DAC is isolated from the controller via optocouplers. Figure 25 illustrates such an interface.
The CS pin of the AD5541/AD5542 can be used to select one of a number of DACs. All devices receive the same serial clock and serial data, but only one device will receive the CS signal at any one time. The DAC addressed will be determined by the decoder. There will be some digital feedthrough from the digital input lines. Using a burst clock will minimize the effects of digital feedthrough on the analog signal channels. Figure 26 shows a typical circuit.

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